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Espressif Systems /ESP32-S2 /UHCI0 /CONF0

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Interpret as CONF0

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IN_RST)IN_RST 0 (OUT_RST)OUT_RST 0 (AHBM_FIFO_RST)AHBM_FIFO_RST 0 (AHBM_RST)AHBM_RST 0 (IN_LOOP_TEST)IN_LOOP_TEST 0 (OUT_LOOP_TEST)OUT_LOOP_TEST 0 (OUT_AUTO_WRBACK)OUT_AUTO_WRBACK 0 (OUT_NO_RESTART_CLR)OUT_NO_RESTART_CLR 0 (OUT_EOF_MODE)OUT_EOF_MODE 0 (UART0_CE)UART0_CE 0 (UART1_CE)UART1_CE 0 (OUTDSCR_BURST_EN)OUTDSCR_BURST_EN 0 (INDSCR_BURST_EN)INDSCR_BURST_EN 0 (MEM_TRANS_EN)MEM_TRANS_EN 0 (SEPER_EN)SEPER_EN 0 (HEAD_EN)HEAD_EN 0 (CRC_REC_EN)CRC_REC_EN 0 (UART_IDLE_EOF_EN)UART_IDLE_EOF_EN 0 (LEN_EOF_EN)LEN_EOF_EN 0 (ENCODE_CRC_EN)ENCODE_CRC_EN 0 (CLK_EN)CLK_EN 0 (UART_RX_BRK_EOF_EN)UART_RX_BRK_EOF_EN

Description

UHCI configuration register

Fields

IN_RST

Set this bit to reset in DMA FSM.
OUT_RST

Set this bit to reset out DMA FSM.
AHBM_FIFO_RST

Set this bit to reset AHB interface cmdFIFO of DMA.
AHBM_RST

Set this bit to reset AHB interface of DMA.
IN_LOOP_TEST

Reserved.
OUT_LOOP_TEST

Reserved.
OUT_AUTO_WRBACK

Set this bit to enable automatic outlink writeback when all the data in TX FIFO has been transmitted.
OUT_NO_RESTART_CLR

Reserved.
OUT_EOF_MODE

This register is used to specify the generation mode of UHCI_OUT_EOF_INT interrupt. 1: When DMA has popped all data from FIFO. 0: When AHB has pushed all data to FIFO.
UART0_CE

Set this bit to link up UHCI and UART0.
UART1_CE

Set this bit to link up UHCI and UART1.
OUTDSCR_BURST_EN

This register is used to specify DMA transmit descriptor transfer mode. 1: burst mode. 0: byte mode.
INDSCR_BURST_EN

This register is used to specify DMA receive descriptor transfer mode. 1: burst mode. 0: byte mode.
MEM_TRANS_EN

1: UHCI transmitted data would be write back into DMA INFIFO.
SEPER_EN

Set this bit to separate the data frame using a special character.
HEAD_EN

Set this bit to encode the data packet with a formatting header.
CRC_REC_EN

Set this bit to enable UHCI to receive the 16 bit CRC.
UART_IDLE_EOF_EN

If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.
LEN_EOF_EN

If this bit is set to 1, UHCI decoder stops receiving payload data when the number of received data bytes has reached the specified value. The value is payload length indicated by UCHI packet header when UHCI_HEAD_EN is 1 or the value is a configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder stops receiving payload data upon receiving 0xC0.
ENCODE_CRC_EN

Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to the end of the payload.
CLK_EN

1: Force clock on for registers. 0: Support clock only when application writes registers.
UART_RX_BRK_EOF_EN

If this bit is set to 1, UHCI stops receiving payload data when a NULL frame is received by UART.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data